`timescale 1ns/1ns

module sin_tb();


reg 	   sys_clk     ;   //系统时钟,50MHz
reg 	   sys_rst_n   ;   //复位信号,低电平有效
reg        digit_signal;
wire [7:0] data_out    ;    //波形输出


always #10 sys_clk = ~sys_clk;

initial begin 
	sys_clk = 0;
	sys_rst_n = 0;
    digit_signal = 1;
	#20
	sys_rst_n = 1;
    
    #4000000
    digit_signal = 0;
    #2000000
    digit_signal = 1;
    #8000000
    digit_signal = 0;   
    #4000000
    digit_signal = 1;     
    
    
    
end



sin  sin_inst
(
    .sys_clk     	(sys_clk),   //系统时钟,50MHz
    .sys_rst_n   	(sys_rst_n),   //复位信号,低电平有效
    .digit_signal   (digit_signal),            
    .data_out       (data_out) //波形输出
);

endmodule
